LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.ALL;

ENTITY logic_unit IS
	PORT ( 	a: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			b: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
			sel: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
			y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END logic_unit ;

ARCHITECTURE logic_unit OF logic_unit IS
BEGIN
	logic_unit: PROCESS (a,b,sel)
	BEGIN	
		CASE sel IS
			WHEN "1000" =>
				--complement a
				y <= NOT a;
			WHEN "1001" =>
				--complement b
				y <= NOT b;
			WHEN "1010" =>
				-- a and b
				y <= a AND b;
			WHEN "1011" =>
				--OR
				y <= a OR b;
			WHEN "1100" =>
				--NAND
				y <= a NAND b;
			WHEN "1101" =>
				--NOR
				y <= a NOR b;
			WHEN "1110" =>
				--XOR
				y <= a XOR b;
			WHEN "1111" =>
				--XNOR
				y <= a XNOR b;
			WHEN OTHERS =>
				y <=a;
		END CASE;
	END PROCESS;
		
END logic_unit ;
